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ISL5416
Pin Descriptions
(Continued)
INTERNAL
NAME
TYPE
PULL-UP/DOWN
DESCRIPTION
JTAG
TDO
O
Test data out
TDI
TMS
TCLK
TRST
I
I
I
I
PULL UP
PULL UP
PULL DOWN
PULL UP
Test data in.
Test mode select.
Test clock.
Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and
there is enough board noise, the JTAG port might get into an unexpected state and stop
communications with the part
OUTPUTS
Aout(15:0)
Bout(15:0)
Cout(15:0)
Dout(15:0)
O
O
O
O
Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section. See Table 24.
Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section.
Parallel Data Output bus C. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section.
Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses. See Data Output Formatter Section and Microprocessor Interface
Section.
Below is the table of the serial output bits allocation for DOUT.
SERIAL OUTPUT BITS ALLOCATION
SER. OUTPUT A SER. OUTPUT B SER. OUTPUT C SER. OUTPUT D
SCLKX *
SSYNCX *
SD1X *
SD2X *
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
DOUT15
* X denotes A, B, C, D as appropriate
Eout(15:0)
CLKO1
CLKO2/
INTRPT
O
O
O
5
A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses.
Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is
programmable.
Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second
clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt
from one or more channels for a sequenced read (FIFO-like) mode. See register GWA = 0000h, bit
13.
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